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Process advanced mems packaging of the IRS method: This is followed by the creation of an indent in the solder and alignment of both chips on the flip-chip tool.

The self-sticking assembly is now ready advanced mems packaging transfer to the reflow oven. In the second approach, a stack of chips or wafers is built whereby the MEMS structure is capped with a chip.

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Different techniques exist for bonding the different chips: The process and materials employed determine the hermeticity and controllability of the cavity ambient.

A drawback for all of these methods is the fact that a trade-off has to be made between the desired ambient gas composition and pressurequality of the bond strength, hermeticity of the seal and process throughput. Microrelay assembly mounted in a ceramic side-brazed package.

Click advanced mems packaging to enlarge image With the indent-reflow-sealing IRS method, sealed cavities can be realized at the wafer level without the drawbacks of the aforementioned approaches. It provides both hermeticity of the cavity seal and controllability of the cavity advanced mems packaging, two features essential for packaging MEMS.


The method is based on a two-chip approach whereby the chips are flip-chip assembled using a solder bond. An optional spacer layer e.

With this approach, the cavity is not etched into the wafer, but instead is defined by the sealing ring created by the spacer and a advanced mems packaging layer.

Other steps of the IRS process flow are the creation of an indent, pre-treatment in a fluorine-based plasma e. This process flow demonstrates one of the key elements of the IRS technique — decoupling of alignment and sealing. To ensure advanced mems packaging safe transfer from the flipchip alignment and bonding tool to the sealing chamber, after alignment, a pre-bonding force is applied on the tool at a slightly elevated temperature.

In the oven, solder reflow and sealing is performed at the desired pressure and gas.

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This makes the IRS technique flexible with respect to the choice of the sealing gas advanced mems packaging the sealing pressure.

The fact that the actual sealing takes place after the flipchip assembly results in a marked cost reduction, because no vacuum flip-chip aligner is needed.


Also, many hermetic packages can undergo reflow simultaneously in the batch oven process. Application advanced mems packaging a Microrelay and Microbolometer We can conclude that the IRS method is a cost-effective zero-level packaging technique that allows protection of vulnerable MEMS devices at an early stage of the packaging process, resulting in a high yield and performance.

The combination advanced mems packaging all these features makes the IRS hermetic packaging technique useful for both space and terrestrial applications. These applications include microrelays Figure 3 and uncooled thermal IR bolometers.

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The IRS method will be illustrated in these two devices. In case of the DC microrelay, the IRS technique has been developed for housing the electrical contacts.

An optimized packaging technique is important because the package influences the microrelay characteristics, particularly the ON-resistance RON advanced mems packaging the ohmic contacts.

With this new zero-level packaging technique, a microrelay with two flip-chip assembled chips at the heart was developed Figure 4.

Wafer-level MEMS packaging

A eutectic bond between electroplated tin-lead solder and gold is used for advanced mems packaging assembly. Fully integrated electromagnetically actu ated microrelays have been successfully fabricated, with the first-level packaging being either ceramic side-brazed or plastic molded packages.


This demonstrates the great potential to use these devices in low-power applications.

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